1. Technical Field
The invention relates to image sensor systems. More particularly, the invention relates to a dual ported memory for a digital image sensor that fundamentally different from the traditional CCD/CMOS image sensors.
2. Description of Related Art
Digital photography is one of the most exciting technologies to have emerged during the twentieth century. With the appropriate hardware and software (and a little knowledge), anyone can put the principles of digital photography to work. Digital cameras, for example, are on the cutting edge of digital photography. Recent product introductions, technological advancements, and price cuts, along with the emergence of email and the World Wide Web, have helped make the digital cameras one of the hottest new categories of consumer electronics products.
Digital cameras, however, do not work in the same way as traditional film cameras do. In fact, they are more closely related to computer scanners, copiers, or fax machines. Most digital cameras use an image sensor or photosensitive device, such as charged-coupled device (CCD) or complementary metal-oxide semiconductor (CMOS) to sense a scene. The photosensitive device reacts to light reflected from the scene and can translate the strength of that reaction into a numeric equivalent. By passing light through red, green, and blue filters, for example, the reaction can be gauged for each separate color spectrum. When the readings are combined and evaluated via appropriate software/hardware, the camera can determine the specific color of each element of the picture. Because the image is actually a collection of numeric data, it can easily be downloaded into a computer and manipulated for more artistic effects.
U.S. Pat. No. 5,461,425 by B. Fowler et al, discloses a new type of image sensors that integrate pixel-level analog-to-digital conversion (ADC) with an area image sensor. Such integration helps lower system cost, power consumption and improve system performance. Among the different schemes for integrating the ADC with an area image sensor, pixel level ADC promises to achieve the lowest power, and the simplest, most process portable and scalable design. The ADC approach described in U.S. Pat. No. 5,461,425 is based on first order sigma delta modulation which has the advantage of requiring fairly simple and robust circuits. Further with the digital values directly provided by each of the pixel elements, the readout of the digital values could be of extremely high. However, the high speed readout can be compromised by subsequent I/O bandwidth due to the limited speed provided by the off-chip memory or computing devices. Further, image processing must be performed by the system after the image data are transferred from the image sensor to a system memory. This consumes computing power, while exacerbating system latency.
What is desired is to provide a sensor architecture that provides the memory function and image processing features without compromising the readout speed from the digital pixels and without requiring significant additional compute power. This desire is fulfilled by the provision of both a memory and a processor on the same substrate as the image sensor.
Unfortunately, integrating an image sensor, which typically has a relatively wide data bus; a processor, which typically has a relatively narrow data bus; and a memory, which typically has a fixed data bus, onto the same substrate adds both latency and complexity to the design. These concerns arise when trying to exchange data between the image sensor, processor, and memory over their respective, mismatched data buses. It would be advantageous to provide an image sensor architecture that accommodates the relative mismatch of bus width between the image sensor, processor, and memory.
The present invention has been made in consideration of the above described challenge and needs and has particular applications to image sensors and system-on-chip (SOC) devices. According to one aspect of the present invention, an image sensor architecture is provided to accommodate the relative mismatch of bus width between the image sensor, processor, and memory. The preferred embodiment of the invention provides a dual-ported memory structure having a relatively wide data port for receiving data from the image sensor and having a relatively narrow data port for communicating data to and from the processor. In one embodiment of the invention, the memory is organized into banks of a specific width. The banks may be accessed sequentially by the processor, such that the bus width is equivalent to the bank width, and the banks may be accessed simultaneously, such that the bus width is equivalent to the combined bank widths. A simple switching means, operating under processor control, reconfigures the memory on the fly.
Accordingly, an important object of the present invention is to provide solutions of accommodating the relative mismatch of bus width between the image sensor, processor, and memory.
Other objects, together with the foregoing are attained in the exercise of the invention in the following description and resulting in the accompanying drawings.